dc.contributor.author | Le Roux, Rikus | |
dc.contributor.author | Van Schoor, George | |
dc.contributor.author | Van Vuuren, Pieter | |
dc.date.accessioned | 2019-09-03T07:10:15Z | |
dc.date.available | 2019-09-03T07:10:15Z | |
dc.date.issued | 2019 | |
dc.identifier.citation | Le Roux, R. et al. 2019. Parsing and analysis of a Xilinx FPGA bitstream for generating new hardware by direct bit manipulation in real-time. South African computer journal, 31(1):80-102. [http://dx.doi.org/10.18489/sacj.v31i1.620] | en_US |
dc.identifier.issn | 1015-7999 | |
dc.identifier.issn | 2313-7835 (Online) | |
dc.identifier.uri | http://hdl.handle.net/10394/33274 | |
dc.identifier.uri | http://sacj.cs.uct.ac.za/index.php/sacj/article/view/620/283 | |
dc.identifier.uri | http://dx.doi.org/10.18489/sacj.v31i1.620 | |
dc.description.abstract | Despite the many advantages run-time reconfiguration of FPGAs brings to the table, its usage is mostly limited to quasi-static applications. This is either due to the throughput of the reconfiguration process, or the time required to create new hardware. In order to optimise the former, the literature proposes a block RAM (BRAM)-based architecture in which a new configuration is stored in localised memory and reconfiguration is facilitated by a controller implemented in the FPGA fabric. The limitation of this architecture is that only a subset of configurations can be stored. When new hardware is required, the slow synthesis process (or a part thereof) has to be repeated for each new configuration. Various third-party tools aim to mitigate this overhead, but since the bitstream is shrouded in obscurity, all rely on a layer of abstraction that make them unusable in real-time. To address this issue, this paper presents a novel method to parse and analyse a Xilinx® FPGA bitstream to extract certain characteristics. It is shown how these characteristics could be used to design and implement a bitstream specialiser, capable of taking a bitstream and modifying the configuration bits of lookup tables in real-time | en_US |
dc.language.iso | en | en_US |
dc.publisher | South African Institute of Computer Scientists and Information Technologists | en_US |
dc.subject | Bitstream analysis | en_US |
dc.subject | Reconfiguration | en_US |
dc.subject | Parsing | en_US |
dc.subject | Direct bitstream manipulation | en_US |
dc.title | Parsing and analysis of a Xilinx FPGA bitstream for generating new hardware by direct bit manipulation in real-time | en_US |
dc.type | Article | en_US |
dc.contributor.researchID | 12134457 - Van Schoor, George | |
dc.contributor.researchID | 10732926 - Van Vuuren, Pieter Andries | |
dc.contributor.researchID | 13077643 - Le Roux, Ronnie Rikus | |