Executing computation intensive algorithms on digital hardware / Gerhard Oosthuizen

Abstract

Even with the advancement of new technology in the field of digital signal processing, it is some times difficult to implement advanced signal processing algorithms on such technologies. When the implementation of these algorithms fails to be as effective as initially planned, the design of the system becomes an optimisation task. More often then not it is possible to review the implementation of an algorithm to run at the desired effectiveness. This task then saves on total system cost or can reduce the time to market. This dissertation investigates implementation methods for computation intensive algorithms. These methods include optimising the code for a digital signal processor and optimising the application executing the algorithm on the processor. Another method investigated is implementing the algorithm on programmable logic to provide a hardware accelerated algorithm for the system. When optimising the code for the signal processor, certain C code optimisations could be done to improve algorithm performance. When the performance gain reached a maximum while optimising the C code, the way the algorithm receives data can be optimised to further the overall application optimisation. Also by implementing the algorithm on programmable logic, such as a Field Programmable Gate Array, greatly improves the effectiveness of the algorithm since the hardware's intrinsic speed is used. However, implementing the algorithm on programmable logic can be a more tedious task than implementing it on a Digital Signal Processor. Even though significantly optimising the algorithm on the Digital Signal Processor, the desired effectiveness was not achieved. The nature of the algorithm required a constant data stream and this proved difficult to achieve. The Field Programmable Gate Array implementation proved more effective and seems to be the most viable option for this type of algorithm. Even though the programmable logic implementation is the implementation of choice for this algorithm, the research on algorithm implementation on a Digital Signal Processor proves that it is possible to implement an algorithm effectively on cheaper hardware. The hardware accelerated algorithm is always a more effective option, but adds development time to the project.